In Lateral Double Diffused Metal Oxide (LDMOS) power transistors, the drain and source semiconductor regions are typically interdigitated regions extending across the LDMOS transistor die and the bonding pads are arranged around the periphery of the LDMOS transistor die. Final metal conductors extend across the drain and source semiconductor regions to connect the semiconductor regions to respective bonding pads.
Since some of the current must flow the length of the drain or source region to the bonding pad, such power transistors have a high on-resistance Rdson which is a significant part of the total device resistance. A high Rdson produces high power dissipation for high currents (15-20 A). Thus, in order to have high current capability, the packaging for such power transistors must be large enough to handle the power dissipation. In other words, by reducing the Rdson, the power transistor can support higher current applications at the same power dissipation level (or transistor area) or can provide lower power dissipation requiring smaller packaging.
Other lateral transistors, such as the TMOS* power transistors supplied by Motorola, Inc., are arranged in similar manner and suffer from the same problems. FNT *TMOS is a trademark of Motorola, Inc.
One solution to reduce the resistance of power devices, such as the LDMOS power transistor, is to have multiple wires bonded to the metal conductors over the semiconductor regions of the power device and to wire bond pads at the periphery of the die so as to reduce the length the current must flow in the metal conductors. Since the current capacity of each wire is limited by its width, a large number of wires are required to reach a high current capability in the region of 15-20 A. The additional bonding pads required for such a plurality of wires considerably increases the size of the power device. Moreover, the cost of manufacturing such a power device is extremely expensive, since each wire has to bonded individually. A further disadvantage of such an arrangement arises due to the fact that as current has to flow some distance through the wires, non-uniform hot spots are produced which reduces the device reliability.
Another solution utilises a thick layer of copper metal deposited on the die above the final metal conductors to reduce the resistance of the power device and replaces the plurality of wires by large aluminium wires bonded on the semiconductor regions. However, the additional deposition step of this solution increases the complexity and cycle time of the manufacturing process which adds significant cost to the integrated power device.
It is therefore an object of the invention to provide an improved semiconductor power device which mitigates the above mentioned problems.